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IW 4093 BN Quad 2-Input NAND Schmitt Trigger IC DIP-14 Package

IW 4093 BN Quad 2-Input NAND Schmitt Trigger IC DIP-14 Package

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(Pack of 10) 1K ohm, 1/4 Watt Resistor Resistance with 5% tolerance

MC14013BCP dual type D flip­flop IC

59.00

The MC14013B dual type D flipflop is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each flipflop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q).

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Description

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Features, Applications
The MC14013B dual type D flip­flop is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. Each flip­flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip­flops for counter and toggle applications.

PDIP­14 P SUFFIX CASE SOIC­14 D SUFFIX CASE 14 14013B AWLYWW MC14013BCP AWLYYWW
Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge­Clocked Flip­Flop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive­going edge of the clock pulse Capable of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load Over the Rated Temperature Range Pin­for­Pin Replacement for CD4013B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to VDD +150 260 Unit °C A WL, L YY, Y WW, W

TSSOP­14 DT SUFFIX CASE SOEIAJ­14 F SUFFIX CASE 1 = Assembly Location = Wafer Lot = Year = Work Week

2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: ­ 7.0 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 

Related Document:-

 MC14013BCP IC Datasheet

* Product Images are shown for illustrative purposes only and may differ from actual product.


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